MILPITAS, Calif. — LSI Logic Corp. today is expected today (July 29) to announce plans to add small programmable-logic cores to its ASICs, a move that mirrors the efforts of FPGA vendors to combine their chips with soft or hard cores. It also marks an industry consensus that programmability, in some form, will be a vital component of future system-on-chip designs.
LSI Logic will offer a maximum of 50,000 programmable gates on an ASIC as part of the company's G12 ASIC architecture, at 0.18-micron (drawn) design rules. LSI will manufacture the embedded-FPGA ASICs at its fabrication facility in Gresham, Ore., and will begin shipping them to beta sites in the first half of next year.
Communications applications are particularly strong drivers of the need for programmability. The shifting landscape of standards, particularly in telecommunications, makes a rigid ASIC undesirable, LSI Logic said. Systems vendors increasingly are asking for some programmable circuitry which could change with the standards tide during manufacturing or even after shipping, said Danny Biran, vice president of strategic marketing for LSI.
"They don't want a large ASIC and a big FPGA next to it," Biran said. "They want to have as much in ASIC as possible because of the cost" of programmable logic gates.
But small bits of programmability won't suffice, according to programmable-logic vendors. If a PLD core is used to shift along with changing standards, it's conceivable that the standards' requirements could outgrow the core, said Craig Leclair, director of component marketing for Altera Corp. (San Jose, Calif.).
More important is the issue of lot sizes. Between increasing mask costs and the additional die area created by process shrinks, the number of devices required for single ASIC orders is rising into the hundreds of thousands of units. PLD vendors claim this trend is pushing many would-be ASIC designers toward FPGAs.
Most PLD suppliers have begun adding cores to programmable devices— sort of the opposite of LSI's approach. Candidates with solutions in this area include Altera, Xilinx Inc., Lucent Microelectronics and Quicklogic Corp.
But LSI Logic officials claim that ASIC customers are looking for only small amounts of programmability — typically 15,000 to 25,000 gates — not the huge arrays being offered in PLD circles. Those feelings echo comments that Bill Harris, engineering manager of Cisco Systems Inc., made earlier this year at FPGA '99, where he said Cisco leans towards ASICs rather than high-density programmable logic.
LSI passed over traditional PLD architectures in favor of an FPGA core from Adaptive Silicon Inc. (Los Gatos, Calif.), a heretofore unknown intellectual-property startup. Adaptive officials designed their programmable logic with embedded functions in mind, resulting in logic arrays amenable to LSI's needs, Biran said.
In terms of die size, for example, the Adaptive core consumes more gates per square millimeter than an ASIC architecture, but is one-fourth the size of a typical FPGA, Biran said. The die size is smaller because Adaptive uses arithmetic logic units in place of look-up tables, he said.
Adaptive's architecture also can be configured in obliquely rectangular shapes — a must for LSI's needs. "In the context of system-on-a-chip, usually you want to have the programmability in the interfaces, along the I/Os," said Biran, who contended that traditional FPGA architectures require a nearly-square layout. But Wim Roelandts, chief executive of Xilinx (San Jose, Calif.), challenged that notion, saying that his company has produced rectangular parts in the past.
LSI did consider licensing FPGA technology from an established outfit, but couldn't find technology that knitted well with ASIC designs, Biran said.
Altera's Leclair said his company isn't interested in teaming up with ASIC suppliers, primarily because of the technical hurdles involved. But Xilinx has had its doors open to the possibility for some time and even discussed an alliance with LSI at one point, Roelandts said.
"We are willing to license our technology to any ASIC company," Roelandts said. "We have been very aggressive in that. We have been pushing very hard, but we haven't found anybody interested in doing that."
Xilinx began studying hybrid ASIC-FPGA chips years ago, Roelandts said, but found limited demand for such chips. And in many cases, Xilinx found that an FPGA placed alongside an ASIC served the same function as an embedded FPGA, but at a much lower cost, Roelandts said.
